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Tera2062 Display Port 1.4 cable BERT
Description
The Tera2062 is Display Port 1.4, Display Port 1.3,Display Port 1.2,Display Port 1.1 cable BERT, provide BER test/debug solution for R&D engineer and manufacture.
The Tera2062 could work mother board with daughter card. User could change daughter card for Display Port Type A cable volume testing.
? 9V power supply, could support remote control in lab.
? Support different PRBS pattern, include PRBS7/PRBS11/PRBS15/PRBS23/PRBS31
? Support real-time BER report for 12 channel (1.25G/2.5G/3.4G/5G/5.4G/6G/8.1G/8.5G/10G/10.7G/11.3G/12G/12.8G )
? Support Alarm-history function, record alarm history at long-term testing
? Support trigger clock output for the eye diagram monitor.
Tera2062 Physical Interface
Power supply
Tera2062 adapter 9V DC power supply. Power supply must not exceed 9V, higher than 9V will damage the analyzer permanently.
Console Interface
Tera2062 use the COM for the remote control and test function.
Traffic Interface
Current Tera2062 have one type daughter card, support Display Port 1.4 Type A connector .
Support three cable simultaneous tests per daughter card.
|
Parameter |
Min |
Typical |
Max |
Unit |
Note |
|
Bit rate |
1.25 |
|
12.8 |
Gb/s |
|
|
Output Swing |
350 |
|
800 |
mVppd |
100Ω differential load peak-peak differential |
|
Jitter（P-P） |
|
|
22.5 |
Ps |
|
|
Jitter（RMS） |
|
2.0 |
3.0 |
Ps |
PRBS^23-1 data at 10 Gbps |
|
Rising/Fall time |
18 |
|
|
Ps |
|
|
Pre-emp |
|
|
12 |
dB |
Post 1 Cursor at Max Swing Setting |
|
Input Swing (at Device) |
100 |
|
1000 |
mV |
Peak-peak differential |
|
Maximum Loss Compensation |
|
25 |
|
dB |
9.95 Gb/s at 10e-12 BER |
|
Input Jitter Tolerance |
|
0.5 |
|
UI |
pre-emphasis |
|
Power supply |
6 |
9 |
9.45 |
V(DC) |
|
|
Power dissipation |
|
|
10 |
W |
|
|
Temperature |
-5 |
|
55 |
oC |
|
|
Store |
-10 |
|
70 |
oC |
|
|
Humility |
5 |
|
90 |
% |
Non-Condensing |
|
RF interface |
K（2.92mm），Compliant SMA |
|
|||
notes: Measurements based on PRBS^23-1 data at 9.95 Gbps.
Trigger Clock Interface
Tera2062 have one trigger clock for the all group port.
10.7 Gbps output eye diagram
Operate procedure
More test or operate procedure please contact sales: Sales@terawan.com
Contact information
http://www.critias.cn
Phone: (+86)755-3284-3656
Cell: (+86)15817448677
Email: sales@terawan.com
The information enclosed (including but not limited to technical specifications, recommendations, and application notes) relating to the products herein is believed to be reliable and accurate and is subject to change without notice. No risk and liability is assumed for use of the products and its applications. Terawan, Inc. reserves the right to change without notice design, specification, form, fit or function relating to the products herein.
Copyright . 2016 Terawan, Inc.
All Rights Reserved
